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3 - axis, 2 g /4 g /8 g /16 g digital mems accelerometer preliminary technical data adxl34 3 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by a nalog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rig hts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.4 61.3113 ? 2012 analog devices, inc. all rights reserved. features multipurpose accelerometer with 10 - to 13 - bit resolution for use in a wide variety of applications digital output accessible via spi (3 - and 4 - wire) and i 2 c built - in motion detection features make tap, double - tap, activity, inactivity, and free - f all detection trivial user - adjustable thresholds interr upts independently mappable to two interrupt pins low power operation down to 23 a and embedded fifo for reducing overall system power wide supply voltage range: 2.0 v to 3.6 v i/o voltage 1.7 v to v s wide operating temperature range (?40c to +85c) 10,000 g shock survival small , thin , pb free, rohs compliant 3 mm 5 mm 1 mm lga package applications handsets gaming and pointing devices hard disk drive ( hdd ) protection general description the ADXL343 is a versatile 3 - axis, digital - output , low g mems accelerometer. selectable measurement range and bandwidth, and configurable , built - in motion detection make i t suitable for sensing acceleration in a wide variety of applications. robustness to 10,000 g of shock and a wide temperature range ( ? 40 c to + 85 c) enable use of the accelerometer even in harsh environments. the ADXL343 measures acceleration with high resolution (13 - bit) measurement at up to 16 g . digital output data is formatted as 16- bit twos complement and is acces sible through either a n spi (3 - or 4 - wire) or i 2 c digital interface. the ADXL343 can measure the static acceleration of gravity in tilt - sensing appli - cations, as well as dynamic acceleration resulting from motion or shock. its high resolution (3.9 m g /lsb) enables measurement of inclination changes less than 1.0 . several special sensing functions are provided. activity and inactivity sensing detect the presence or lack of motion . tap sensing detects single and double taps in any direction . free - fall sensing detects if the device is falling. these functions can be mapped individually to either of two interrup t output pins. an integrat ed memory management system with a 32 - level first in, first out ( fifo ) buffer can be used to store data to mini mize host processor activity and lower overall system power consumption . the ADXL343 is supplied in a small, thin , 3 mm 5 mm 1 mm, 14- terminal , plastic package. functional block dia gram 3-axis sensor sense electronics digital filter ADXL343 power management control and interrupt logic serial i/o int1 v s v dd i/o int2 sda/sdi/sdio sdo/alt address scl/sclk gnd adc 32 level fifo cs 10627-001 figure 1.
ADXL343 preliminary technical data rev. pra | page 2 of 36 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? package information .................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 11 ? power sequencing ...................................................................... 11 ? power savings ............................................................................. 12 ? serial communications ................................................................. 13 ? spi ................................................................................................. 13 ? i 2 c ................................................................................................. 16 ? interrupts ..................................................................................... 18 ? fifo ............................................................................................. 19 ? self-test ....................................................................................... 20 ? register map ................................................................................... 21 ? register definitions ................................................................... 22 ? applications information .............................................................. 26 ? power supply decoupling ......................................................... 26 ? mechanical considerations for mounting .............................. 26 ? tap detection .............................................................................. 26 ? threshold .................................................................................... 27 ? link mode ................................................................................... 27 ? sleep mode vs. low power mode............................................. 28 ? offset calibration ....................................................................... 28 ? using self-test ............................................................................ 29 ? data formatting of upper data rates ..................................... 30 ? noise performance ..................................................................... 31 ? operation at voltages other than 2.5 v ................................ 31 ? offset performance at lowest data rates ............................... 32 ? axes of acceleration sensitivity ............................................... 33 ? layout and design recommendations ................................... 34 ? outline dimensions ....................................................................... 35 ?
preliminary technical data ADXL343 rev. pra | page 3 of 36 specifications t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v, acceleration = 0 g , c s = 1 0 f tantalum, c i / o = 0.1 f, output data rate ( odr ) = 800 hz, unless otherwise noted. all minimum and maximum specifications are guaranteed. typical specifications are not guaranteed. table 1 . parameter test conditions /comments min typ 1 max unit sensor input each axis measurement range user selectable 2, 4, 8, 16 g nonlinearity percentage of full scale 0.5 % inter - axis alignment error 0.1 degrees cross - axis sensitivity 2 1 % output resolution each axis all g ranges 10- bit resolution 10 bi ts 2 g range full resolution 10 bits 4 g range full resolution 11 bits 8 g range full resolution 12 bits 16 g range full resolution 13 bits sensitivity each axis sensitivity at x out , y out , z out all g ranges, full resolution 256 ls b/ g 2 g , 10 - bit resolution 256 lsb/ g 4 g , 10 - bit resolution 128 lsb/ g 8 g, 10- bit resolution 64 lsb/ g 16 g, 10- bit resolution 32 lsb/ g sensitivity deviation from ideal all g ranges 1.0 % scale factor at x out , y out , z out all g rang es, full resolution 3.9 m g/ lsb 2 g , 10 - bit resolution 3.9 m g/ lsb 4 g, 10- bit resolution 7.8 m g/ lsb 8 g, 10- bit resolution 15.6 m g/ lsb 16 g, 10 - bit resolution 31.2 m g/ lsb sensitivity change due to temperature 0.01 %/c 0 g offset each axis 0 g output deviation from ideal, x -, y -, z - axes 35 m g 0 g offset vs. temperature for x -, y -, z - axes 0. 8 m g /c noise x -, y -, z - axes odr = 100 hz for 2 g , 10 - bit resolution or all g - ranges, full resolution 1.1 lsb rms out put data rate and bandwidth user selectable output data rate (odr) 3 , 4 , 5 0.1 3200 hz self - test 6 output change in x - axis 0.20 2.10 g output change in y - axis ? 2.10 ? 0.20 g output change in z - axis 0.30 3.40 g power supply operating voltage range (v s ) 2.0 2.5 3.6 v interface voltage range (v dd i/o ) 1.7 1.8 v s v supply current odr 100 hz 140 a odr < 10 hz 30 a standby mode leakage c urrent 0.1 a turn - on and wake - up time 7 odr = 3200 hz 1.4 ms
ADXL343 preliminary technical data rev. pra | page 4 of 36 parameter test conditions /comments min typ 1 max unit temperature operating temperature range ? 40 +85 c weight device weight 30 m g 1 the t ypical specification s shown are f or at least 68% of the population of parts and are based on the worst case of mean 1 , except for 0 g output and sensitivity, which represent s the target value. for 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean 1 . 2 cross - axis sensitivity is defined as c oupling between any two axes. 3 bandwidth is the ?3 db frequency and is half the output data rate, bandwidth = odr/2. 4 the output format for the 3200 hz and 1600 hz odrs is different than the output format for the remaining odrs. this differenc e is descri bed in the data formatting of upper data rates section. 5 output data rates below 6.25 hz exhibit additional offset shift with increased temperature, depending on selected output data rate. refer to the offset performa nce at lowest data rates section for details. 6 self - test change is defined as the output ( g ) when the self_test bit = 1 (in the data_format register, address 0x31) minus the output ( g ) when the self_test bit = 0. due to device filtering, t he output reaches its final value after 4 when enabling or disabling self - test, where = 1/(data rate). the part must be in normal power operation (low_power bit = 0 in the bw_rate register, address 0x2c) for self - test to operate correctly. 7 turn - on and wake - up times are determined by the user - defined bandwidth. at a 100 hz data rate, the turn - on and wake - up times are each approximately 11.1 ms. for other data rates, the turn - on and wake - up times are each approximately + 1.1 in milliseconds, where = 1/(data rate).
preliminary technical data ADXL343 rev. pra | page 5 of 36 absolute maximum ratings table 2. parameter rating acceleration any axis, unpowered 10,000 g any axis, powered 10,000 g v s ?0.3 v to +3.9 v v dd i/o ?0.3 v to +3.9 v digital pins ?0.3 v to v dd i/o + 0.3 v or 3.9 v, whichever is less all other pins ?0.3 v to +3.9 v output short-circuit duration (any pin to ground) indefinite temperature range powered ?40c to +105c storage ?40c to +105c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 3. package characteristics package type ja jc device weight 14-terminal lga 150c/w 85c/w 30 mg package information the information in figure 2 and table 4 provide details about the package branding for the ADXL343 . 3 4 3 b # y w w v v v v c n t y 10627-102 figure 2. product information on package (top view) table 4. package branding information branding key field description 343b part identifier for the ADXL343 # rohs-compliant designation yww date code vvvv factory lot code cnty country of origin esd caution
ADXL343 preliminary technical data rev. pra | page 6 of 36 pin configuration and function descriptions cs sda/sdi/sdio sdo/alt address reserved nc int2 int1 v dd i/o gnd reserved gnd gnd v s 13 12 11 10 9 8 1 2 3 4 +x +y +z 5 6 14 7 scl/sclk ADXL343 top view (not to scale) 10627-002 notes 1. nc = no internal connection. figure 3 . pin configuration (top view) table 5 . pin function descriptions pin no. mnemonic description 1 v dd i/o digital interface supply voltage. 2 gnd this pi n m ust be connected to ground. 3 r eserved reserved. this pin must be connected to v s or left open. 4 gnd this pin must be connected to ground. 5 gnd this pin must be connected to ground. 6 v s supply voltage. 7 cs chip select. 8 int1 interrupt 1 output. 9 int2 interrupt 2 output. 10 nc not internally connected. 11 r eserved reserved. this pin must be connected to ground or left open. 12 sdo/alt address serial data output (spi 4 - wire)/alternate i 2 c address select (i 2 c). 13 sda/ sdi/sdio serial data (i 2 c)/serial data input (spi 4 - wire)/serial data input and output (spi 3 - wire). 14 scl/sclk serial communications clock. scl is the clock for i 2 c, and sclk is the clock for spi.
preliminary technical data ADXL343 rev. pra | page 7 of 36 typical performance characte ristics 2 0 4 6 8 10 12 14 16 18 20 ?150 ?100 ?50 0 50 100 150 zero g offset (m g) percent of popul a tion (%) 10627-206 figure 4 . zero g offset at 25c, v s = 2.5 v , all axes 2 0 4 6 8 10 12 14 16 18 20 ?150 ?100 ?50 0 50 100 150 zero g offset (m g) percent of popul a tion (%) 10627-209 figure 5. zero g offset at 25c, v s = 3.3 v , all axes 0 5 10 15 20 25 30 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 zero g offset temper a ture coefficient (m g /c) percent of popul a tion (%) 10627-210 figure 6. zero g offset temperature coefficient , v s = 2.5 v , all axes ?150 ?100 ?50 0 50 100 150 ?40 ?20 0 20 40 60 80 100 temper a ture (c) output (m g) n = 16 a vdd = dvdd = 2.5v 10627-213 figur e 7. x - axis zero g offset vs. temperature eight parts soldered to pcb, v s = 2.5 v ?150 ?100 ?50 0 50 100 150 ?40 ?20 0 20 40 60 80 100 temper a ture (c) output (m g) n = 16 a vdd = dvdd = 2.5v 10627-214 figure 8. y - axis zero g offset vs. temperature eight parts soldered to pcb, v s = 2.5 v ?150 ?100 ?50 0 50 100 150 ?40 ?20 0 20 40 60 80 100 temper a ture (c) output (m g) n = 16 a vdd = dvdd = 2.5v 10627-215 figure 9. z - axis zero g offset vs. temperature eight parts soldered to pcb, v s = 2.5 v
ADXL343 preliminary technical data rev. pra | page 8 of 36 0 5 10 15 20 25 30 35 40 45 50 55 230 234 238 242 246 250 254 258 262 266 270 274 278 282 sensitivit y (lsb/ g) percent of popul a tion (%) 10627-218 figure 10 . sensitivity at 25c, v s = 2.5 v, full resolution , all axes 0 5 10 15 20 25 30 35 40 ?0.02 ?0.01 0 0.01 0.02 sensitivit y temper a ture coefficient (%/c) percent of popul a tion (%) 10627-219 figure 11 . sensitivity temperature coeffic ient, v s = 2.5 v , all axes 0 5 10 15 20 25 100 1 10 120 130 140 150 160 170 180 190 200 current consumption (a) percent of popul a tion (%) 10627-231 figure 12 . current consumption at 25c, 100 hz output data rate, v s = 2.5 v 0 20 40 60 80 100 120 temper a ture (c) 230 235 240 245 250 255 260 265 270 275 280 sensitivit y (lsb/ g) ?40 ?20 10627-222 figure 13 . x - axis sensitivity vs. temperature eight parts soldered to pcb , v s = 2.5 v, full r esolution 230 235 240 245 250 255 260 265 270 275 280 temper a ture (c) sensitivit y (lsb/ g) 0 20 40 60 80 100 120 ?40 ?20 10627-223 figure 14 . y - axis sensitivity vs. temperature eight parts soldered to pcb , v s = 2.5 v, full resolution 230 235 240 245 250 255 260 265 270 275 280 temper a ture (c) sensitivit y (lsb/ g) 0 20 40 60 80 100 120 ?40 ?20 10627-224 figure 15 . z - axis sensitivity vs. temperature eight parts soldered to pcb , v s = 2.5 v, full resolution
preliminary technical data ADXL343 rev. pra | page 9 of 36 temper a ture (c) 230 235 240 245 250 255 260 265 270 275 280 sensitivit y (lsb/ g) 0 20 40 60 80 100 120 ?40 ?20 10627-225 figure 16 . x - axis sensitivity vs. temperature eight parts soldered to pcb , v s = 3.3 v, full resolution 0 20 40 60 80 100 120 temper a ture (c) 230 235 240 245 250 255 260 265 270 275 280 sensitivit y (lsb/ g) ?40 ?20 10627-226 figure 17 . y - axis sensitivity vs. temperature eight parts soldered to pcb , v s = 3.3 v, full resolution 0 20 40 60 80 100 120 temper a ture (c) 230 235 240 245 250 255 260 265 270 275 280 sensitivit y (lsb/ g) ?40 ?20 10627-227 figure 18 . z - axis sensitivity vs. temperature eight parts soldered to pcb , v s = 3.3 v, full resolution 0 10 20 30 40 50 60 0.2 0.5 0.8 1.1 1.4 1.7 2.0 self-test response ( g) percent of popul a tion (%) 10627-228 figure 19 . x - axis self - test response at 25c, v s = 2.5 v 0 10 20 30 40 50 60 ?0.2 ?0.5 ?0.8 ?1.1 ?1.4 ?1.7 ?2.0 self-test response ( g) percent of popul a tion (%) 10627-229 fi gure 20 . y - axis self - test response at 25c, v s = 2.5 v 0 10 20 30 40 50 60 0.3 0.9 1.5 2.1 2.7 3.3 self-test response ( g) percent of popul a tion (%) 10627-230 figure 21 . z - axis self - test response at 25c, v s = 2.5 v
ADXL343 preliminary technical data rev. pra | page 10 of 36 0 20 40 60 80 100 120 140 160 1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200 output d at a r a te (hz) current consumption (a) 10627-232 figure 22 . current consumption vs. output data rate at 25c 10 parts, v s = 2.5 v 0 50 100 150 200 2.0 2.4 2.8 3.2 3.6 supp l y vo lt age (v) supp l y current (a) 10627-233 figure 23 . supply current vs. supply voltage, v s at 25c
preliminary technical data ADXL343 rev. pra | page 11 of 36 theory of operation the ADXL343 is a complete 3 - axis acceleration measurement system with a selec table measurement range of 2 g, 4 g, 8 g , or 16 g . it measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, that allows the device to be used as a tilt sensor. the sensor is a polysilicon surface - m icromachined structure built on top of a silicon wafer. polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against forces due to applied acceleration. deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. acceleration deflects the proof mass and unbalances the differential capacitor, resulting in a sensor output whose ampli - tude is proportional to acceleration. phas e - sensitive demodulation is used to determine the magnitude and polarity of the acceleration . power sequencing power can be applied to v s or v dd i/o in any sequence without damaging the ADXL343 . all po ssible power - on mode s are summarized in table 6 . the interface voltage level is set with the interface supply voltage , v dd i/o , which must be present to ensure that the ADXL343 does not crea te a conflict on the communication bus. for single - supply operation, v dd i/o can be the same as the main supply, v s . i n a dual - supply application, however, v dd i/o can differ from v s to accommodate the desired interface voltage , as long as v s is greater th an or equal to v dd i/o . after v s is applied, the device enters standby mode, where power consumption is minimized and the device waits for v dd i/o to be applied and for the command to enter measurement mode to be received. (this command can be initiated b y setting the measure bit (bit d3) in the power_ctl register (address 0x2d).) in addition, while the device is in standby mode , any register can be written to or read from to configure the part. it is recommended to configure the device in standby mode and then to enable measurement mode. clearing the measure bit returns the device to the standby mode . table 6 . power sequencing condition v s v dd i/o description power off off off the device is completely off, but there is a potent ial for a communication bus conflict. bus disabled on off the device is on in standby mode, but communication is unavailable and create s a conflict on the communication bus. the duration of this state should be minimized during power - up to prevent a con flict. bus enabled off on no functions are available, but the device does not create a conflict on the communication bus. standby or measurement on on at power - up, the device is in standby mode, awaiting a command to enter m easurement mode, and all sens or functions are off. after the device is instructed to enter measurement mode, all sensor functions are available.
ADXL343 preliminary technical data rev. pra | page 12 of 36 power saving s power modes the ADXL343 automatically modulates its power consumption in p roportion to its output data rate , as outlined in table 7 . if additional power savings is desired, a lower power mode is available. in this mode, the internal sampling rate is reduced , allowing for power savings in the 12.5 hz to 400 hz data rate range at the expense of slightly greater noise. to enter low power mode, set the low_power bit (bit 4) in the bw_rate register (address 0x2c) . the current consumption in low power mode is shown in table 8 for cas es where there is an advantage to using low power mode. use of low power mode for a data rate not shown in table 8 does not provide any advantage over the same d ata rate in normal power mode. therefore, it is recommended that onl y data rates shown in table 8 are used in low power mode. the current consumption values shown in table 7 and table 8 are for a v s of 2.5 v . table 7 . ty pical current consumption vs . data rate (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) output data rate (hz) bandwidth (hz) rate code i dd (a) 3200 1600 1111 140 1600 800 1110 90 800 400 1101 140 400 200 1100 140 200 100 1011 140 100 50 1010 140 50 25 1 001 90 25 12.5 1000 60 12.5 6.25 0111 50 6.25 3.13 0110 45 3.13 1.56 0101 40 1.56 0.78 0100 34 0.78 0.39 0011 23 0.39 0.20 0010 23 0.20 0.10 0001 23 0.10 0.05 0000 23 table 8 . typical current consumption vs . data rate, l ow power mode (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) output data rate (hz) bandwidth (hz) rate code i dd (a) 400 200 1100 90 200 100 1011 60 100 50 1010 50 50 25 1001 45 25 12.5 1000 40 12.5 6.25 0111 34 auto sleep mode additional power can be sa ved if the ADXL343 automatically switches to sleep mode during periods of inactivity. to enable this feature, set the thresh_inact register (address 0x25) and the time_inact register (address 0x26) each to a va lue that signifies inactivity (the appropriate value depends on the application), and then set the auto_sleep bit (bit d4) and the link bit (bit d5) in the power_ctl register (address 0x2d). current consumption at the sub - 12.5 hz data rates that are used in this mode is typically 23 a for a v s of 2.5 v . standby mode for even lower power operation, standby mode can be used. in standby mode, current consumption is reduced to 0. 1 a (typical). in this mode, no measurements are made. standby mode is entered by clearing the measure bit (bit d3) in the power_ctl register (address 0x2d). placing the device into standby mode preserves the contents of fifo .
preliminary technical data ADXL343 rev. pra | page 13 of 36 serial communication s i 2 c and spi digital communications are available. in both cases, the ADXL343 operates as a slave. i 2 c mode is enabled if the cs pin is tied high to v dd i/o . the cs pin should always be tied high to v dd i/o or be driven by an external controller be cause there is no default mode if the cs pin is left unconnected. therefore, not taking these precautions may result in an inability to communicate with the part. in spi mode, the cs pin is controlled by the bus master. in both spi and i 2 c modes of operation, data transmitted from the ADXL343 to the master device should be ignored during writes to the ADXL343 . spi for spi , either 3 - or 4 - wire configuration is possible, as shown in the connection diagrams in figure 24 and figure 25 . clearing the spi bit (bit d6) in the data_format register (address 0x31) selects 4 - wire m ode, whereas setting the spi bit selects 3 - wire mode. the maximum spi clock speed is 5 mhz with 100 pf maximum loading, and the timing scheme follows clock polarity (cpol) = 1 and clock phase (cpha) = 1. if power is applied to the ADXL343 before the clock polarity and phase of the host processor are configured, the cs pin should be brought high before changing the clock polarity and phase. when using 3 - wire spi, it is recommended that the sdo pin be either pulled up to v dd i/o or pulled down to gnd via a 10 k? resistor . processor cs mosi miso sclk ADXL343 cs sdio sdo sclk 10627-004 figure 24 . 3 - wire spi connection diagram processor cs mosi miso sclk ADXL343 cs sdi sdo sclk 10627-003 figure 25 . 4 - wire spi connection diagram cs is the se rial port enable line and is controlled by the spi master. this line must go low at the start of a transmission and high at the end of a transmission, as shown in figure 27 . sclk is the serial port clock and is supplied by the spi master. sclk should idle high during a period of no transmission. sdi and sdo are the serial data input and output, respectively. data is updated on the falling edge of sclk and should be sampled on the rising edge of sclk. to read or write multiple bytes in a single transmission, the multiple - byte bit, located after the r/ w bit in the first byte transfer (mb in figure 27 to figure 29 ), must be set. after the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the ADXL343 to point to the next register for a read or write. this shifting continues until the clock pulses cease and cs is deasserted. to perform reads or writes on different, nonsequential registers, cs must be deasserted between transmissions and the new register must be addressed separately . the timing diagram for 3 - wire spi reads or writes is shown in figure 29. the 4 - wire equivalents for spi writes and reads are shown in figure 27 and figure 28, respectively. for correct operation of the part, the logic thresholds and timing parameters in table 9 and table 10 must be met at all times. use of the 3200 hz and 1600 hz output data rates is only recommended with spi communication rates greater than or equal to 2 mhz. the 800 hz output data rate is recommended only for c ommunication speeds greater than or equal to 400 khz , and the remaining data rates scale proportionally. for example, the minimum recommended communication speed for a 200 hz output da ta rate is 100 khz. operation at an output data rate above the recommended maximum may result in undesirable effects on the acceleration data , including missing samples or additional noise. preventing bus traffic errors the ADXL343 cs pin is used both for initiating spi transac - tions and for enabling i 2 c mode. when the ADXL343 is used on a spi bus with multiple devices, its cs pin is held high while the master communicates with the other devices. there may be conditions where a spi command transmitted to another device looks like a valid i 2 c command. in this case, the ADXL343 interpret s this as an attempt to communicate in i 2 c mode, and may interfere with other bus traffic. unless bus traffic can be adequately controlled to assure such a condition never occurs, it is recommended to add a logic gate in front of the sdi pin as shown in figure 26 . this or gate hold s the sda line high when cs is high to prevent spi bus traffic at the ADXL343 from appearing as an i 2 c start comm and. not e that this recommendation applies only in cases where the ADXL343 is used on a spi bus with multiple devices. processor mosi miso sclk cs ADXL343 cs sdio sdo sclk 10627-104 figure 26 . recommended spi connection diagram when using multiple spi devices on a single bus
ADXL343 preliminary technical data rev. pra | page 14 of 36 t delay t setup t hold t sdo x x x w mb a5 a0 d7 d0 x x x address bits data bits t sclk t m t s t quiet t dis t cs,dis sclk sdi sdo cs 10627-017 figure 27 . spi 4 - wire write cs x x x r mb a5 a0 d7 d0 x x x address bits data bits t dis sclk sdi sdo t quiet t cs,dis t sdo t setup t hold t delay t sclk t m t s 10627-018 figure 28 . spi 4 - wire read cs t delay t setup t hold t sdo r/w mb a5 a0 d7 d0 address bits data bits t sclk t m t s t quiet t cs,dis sclk sdio sdo notes 1. t sdo is only present during reads. 10627-019 figure 29 . spi 3 - wire read/write
preliminary technical data ADXL343 rev. pra | page 15 of 36 table 9 . spi digital input/output limit 1 parameter test conditions min max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage (v ih ) 0.7 v dd i/o v low level input current (i il ) v in = v dd i/o 0.1 a high level input current (i ih ) v in = 0 v ? 0.1 a digital output low level output voltage (v ol ) i ol = 10 ma 0.2 v dd i/o v high level output voltage (v oh ) i oh = ? 4 ma 0.8 v dd i/o v low level output current (i ol ) v ol = v ol, max 10 ma high level output current (i oh ) v oh = v o h, min ? 4 ma pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf 1 limits based on characterization results, not production tested. table 10 . spi timing (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) 1 limit 2 , 3 parameter min max unit description f sclk 5 mhz spi clock frequency t sclk 200 n s 1/(spi clock frequency) mark - space ratio for the sclk input is 40/60 to 60/40 t delay 5 ns cs falling edge to sclk falling edge t quiet 5 ns sclk rising edge to cs rising edge t dis 10 ns cs rising edge to sdo disabled t cs,dis 150 ns cs deassertion between spi communications t s 0.3 t sclk ns sclk low pulse width (space) t m 0.3 t sclk ns sclk high pulse width (mark) t setup 5 ns sdi valid before sc lk rising edge t hold 5 ns sdi valid after sclk rising edge t sdo 40 ns sclk falling edge to sdo/sdio output transition t r 4 20 ns sdo/sdio output high to output low transition t f 4 20 ns sdo/sdio output low to o utput high transition 1 the cs , sclk, sdi, and sdo pins are not internally pulled up or down; they must be driven for proper operation. 2 limits based on characterization results, characterized with f sclk = 5 mhz and bus load capacitance of 100 pf; not production tested. 3 the timing values are measured corresponding to the input thresholds (v il and v ih ) given in table 9 . 4 output rise and fall ti mes measured with capacitive load of 150 pf.
ADXL343 preliminary technical data rev. pra | page 16 of 36 i 2 c with cs tied high to v dd i/o , the ADXL343 is in i 2 c mode, requiring a simple 2 - wire connection , as shown in figure 30. the ADXL343 conforms to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007 , available from nxp semiconductor. it supports standard (100 khz) and fast (400 khz) data transfer modes if the bus paramet ers given in table 11 and table 12 are met . single - or multiple - byte read s /writes are supported , as shown in figure 31 . with the alt address pin high , the 7 - bit i 2 c address fo r the device is 0x1d, followed by the r/ w bit. this translates to 0x3a for a write and 0x3b for a read. an alternate i 2 c address of 0x53 (followed by the r/ w bit) can be chosen by grounding the alt address pin ( p in 12). this translates to 0xa6 for a write and 0xa7 for a read. there are no internal pull - up or pull - dow n resistors for any unused pins; therefore , there is no known state or default state for the cs or alt address pin if left floa ting or unconnected. i t is required that the cs pin be connected to v dd i/o and that the alt address pin be connected to either v dd i/o or gnd when using i 2 c. due to communication speed limitations, the maximum output data rate when using 400 khz i 2 c is 800 hz and scales linearly with a change in the i 2 c communication speed. for example, using i 2 c at 100 khz limit s the maximum odr to 200 hz. operation at an output data rate above the recommended maxi - mum may result in undesirable effe ct on the acceleration data , including missing samples or additional noise. processor d in/out d out r p v dd i/o r p ADXL343 cs sda alt address scl 10627-008 figure 30 . i 2 c connection diagram (address 0x53) if other devices are connected to the same i 2 c bus, the nominal operating voltage level of these other devices cannot exceed v dd i/o by more than 0.3 v. external p ull - up resistors, r p , are necessary for proper i 2 c operation. refer to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007, when selecting pull - up resistor values to ensure pro per operation . table 11. i 2 c digital input/output limit 1 parameter test conditions min max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage (v ih ) 0.7 v dd i/o v low level i nput current (i il ) v in = v dd i/o 0.1 a high level input current (i ih ) v in = 0 v ? 0.1 a digital output low level output voltage (v ol ) v dd i/o < 2 v, i ol = 3 ma 0.2 v dd i/o v v dd i/o 2 v, i ol = 3 ma 400 mv low level output current (i ol ) v ol = v ol, max 3 ma pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf 1 limits based on characterization results; not production tested. master start slave address + write register address slave ack ack ack master start slave address + write register address slave ack ack ack ack master start slave address + write register address stop slave ack ack master start start 1 start 1 slave address + write register address nack stop slave ack ack data stop ack single-byte write multiple-byte write data data multiple-byte read slave address + read slave address + read ack data data data stop nack ack single-byte read 10627-033 1 this start is either a restart or a stop followed by a start. notes 1. the shaded areas represent when the device is listening. figure 31 . i 2 c device addressing
preliminary technical data ADXL343 rev. pra | page 17 of 36 table 12. i 2 c timing (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) limit 1 , 2 parameter min max unit description f scl 400 khz scl clock frequency t 1 2.5 s scl cycle time t 2 0.6 s t high , scl high time t 3 1.3 s t low , scl low time t 4 0.6 s t hd, sta , start/repeated start condition hold time t 5 100 ns t su, dat , data setup time t 6 3 , 4 , 5 , 6 0 0.9 s t hd, dat , data hold time t 7 0.6 s t su, sta , setup time for repea ted start t 8 0.6 s t su, sto , stop condition setup time t 9 1.3 s t buf , bus - free time between a stop condition and a start condition t 10 300 ns t r , rise time of both scl and sda when receiving 0 ns t r , rise time of both scl and sda when receiv ing or transmitting t 11 300 ns t f , fall time of sda when receiving 25 0 ns t f , fall time of both scl and sda when transmitting c b 400 pf capacitive load for each bus line 1 limits based on characterization results, with f scl = 400 khz and a 3 ma sink current; not production tested. 2 all values referred to the v i h and the v il levels given in table 11. 3 t 6 is the data hold time that is measured from the falling edge of scl. it applies to data in transmission and acknowledge. 4 a transmitting device must internally provide an output hold time of at least 300 ns for the sda signal (with respect to v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. 5 the maximum t 6 value must be met only if the device does not stretch the low period (t 3 ) of the scl signal. 6 the maximum value for t 6 is a function of the clock low time (t 3 ), the clock rise time (t 10 ), and the minimum data setup time (t 5(min) ). this value is calculated as t 6(max) = t 3 ? t 10 ? t 5(min) . sda t 9 scl t 3 t 10 t 1 1 t 4 t 4 t 6 t 2 t 5 t 7 t 1 t 8 st art condition repe a ted st art condition st op condition 10627-034 figure 32 . i 2 c timing diagram
ADXL343 preliminary technical data rev. pra | page 18 of 36 interrupts th e ADXL343 provides two output pins for driving interrupts: int1 and int2. both interrupt pins are push - pull, low impedance pins with output specifications shown in table 13. the defau lt configuration of the interrupt pins is active high. this can be changed to active low by setting the int_invert bit in the data_format (address 0x31) register. all functions can be used simultaneously, with the only limiting feature being that some fu nctions may need to share interrupt pins. interrupts are enabled by setting the appropriate bit in the int_enable register (address 0x2e) and are mapped to either the int1 or int2 pin based on the contents of the int_map register (address 0x2f) . when ini tially configuring the interrupt pins, i t is recommended that the functions and interrupt mapping be done before enabling the interrupts. when changing the configuration of an interrupt, it is recommended that the interrupt be disabled first , by clearing t he bit corresponding to that function in the int_enable register, and then the function be reconfigured before enabling the interrupt again. configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an i nterrupt before desired . the interrupt functions are latched and cleared by either reading the data registers ( address 0x32 to address 0x37) until the interrupt condition is no longer val id for the data - related interrupts or by reading the int_source regi ster ( address 0x30) for the remaining interrupts. this section describes the interrupts that can be set in the int_enable register and monitored in the int_source register. data_ready the d ata_ready bit is set when new data is available and is cleared wh en no new data is available. single_tap the single _tap bit is set when a single acceleration event that is greater than the value in the thresh_tap register (address 0x1d) occurs for less time than is specified in the dur register (address 0x21) . double_ta p the double_ tap bit is set when two acceleration events that are greater than the value in the thresh_tap register (address 0x1d) occur for less time than is specified in the dur register (address 0x21) , with the second tap starting after the time specif ied by the latent register (address 0x22) but within the time specified in the window register (address 0x23) . see the tap detection section for more details. activity the activity bit is set when acceleration greater than the va lue stored in the thresh_act register (address 0x24) is experienced on any participating axis, set by the act_inact_ctl register (address 0x27) . inactivity the inactivity bit is set when acce leration of less than the value stored in the thresh_inact regist er (address 0x25) is experienced for more time than is specified in the time_inact register (address 0x26) on all participating axes, as set by the act_inact_ctl register (address 0x27) . the maximum value for time_inact is 255 sec . free_fall the free_fall bit is set when acceleration of less than the value stored in the thresh_ff register (address 0x28) is experienced for more time than is specified in the time_ff register (address 0x29) on all axes (logical and). the free_fall interrupt differs from the in activity interrupt as follows: all axes always participate and are logically anded, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc - coupled . watermark the watermark bit is set when the number of samples in fifo equals the value stored in the samples bits (register fifo_ctl, address 0x38) . the watermark bit is cleared automatically when fifo is read , and the content return s to a value below the value stored in the samples bits . table 13. interrupt pin digital output limit 1 parameter test conditions min max unit digital output low level output voltage (v ol ) i ol = 300 a 0.2 v dd i/o v high level output voltage (v oh ) i oh = ?150 a 0.8 v dd i/o v low level output current (i ol ) v ol = v ol, max 300 a high level output current (i oh ) v oh = v oh, min ? 150 a pin capacitance f in = 1 mhz, v in = 2.5 v 8 pf rise/fall time rise time (t r ) 2 c load = 150 pf 210 ns fall ti me (t f ) 3 c load = 150 pf 150 ns 1 limits based on characterization results, not production tested. 2 rise time is measured as the transition time from v ol, max to v oh, min of the interrupt pin. 3 fall time is measured as the transition time from v oh, min to v ol, max of the interrupt pin.
preliminary technical data ADXL343 rev. pra | page 19 of 36 overrun the overrun bit is set when new data replaces unread data. the precise operation of the overrun function depends on the fifo mode. in bypass mode, the overrun bit is set when new data replaces unread data in th e datax, datay, and dataz registers (address 0x32 to address 0x37). in all other modes, the overrun bit is set when fifo is filled. the overrun bit is automatically cleared when the contents of fifo are read. fifo the ADXL343 contains an embedded memory management system with a 32- level fifo memory buffer that can be used to minimize host processor burden. this buffer has four modes: bypass, fifo, stream, and trigger (see table 22 ). ea ch mode is selected by the settings of the fifo_mode bits (bits[d7:d6]) in the fifo_ctl re gister (address 0x38) . if use of the fifo is not desired, the fifo should be placed in bypass mode . bypass mode in bypass mode, fifo is not operational and , therefor e, remains empty. fifo mode in fifo mode, data from measurements of the x - , y - , and z - axes are stored in fifo. when the number of samples in fifo equals the level specified in the samples bits of the fifo_ctl register (address 0x38 ), the watermark interru pt is set. fifo continue s accumulating samples until it is full (32 samples from measurements of the x - , y - , and z - axes ) and then stop s collecting data. after fifo stops collecting data , the device continues to operate ; therefore, features such as tap dete ction can be used after fifo is full. the watermark interrupt continue s to occur until the number of samples in fifo is less than the value stored in the samples bits of the fifo_ctl register. stream mode in stream mode, data from measurements of the x - , y - , and z - axes are stored in fifo. when the number of samp les in fifo equals the level specified in the samples bits of the fifo_ctl register (address 0x38) , the watermark interrupt is set. fifo continue s accumulating samples and hold s the latest 32 samples from measurements of the x - , y - , and z - axes , discarding older data as new data arrives. the watermark interrupt continue s occur ring until the number of samples in fifo is less than the value stored in the samples bits of the fifo_ctl register. trigger mo de in trigger mode , fifo accumulates samples, holding the latest 32 samples from measurements of the x - , y - , and z - axes . after a trigger event occurs and an interrupt is sent to the int1 or int2 pin ( determined by the trigger bit in the fifo_ctl register ), fifo keep s the last n samples (where n is the value specified by the samples bits in the fifo_ctl register) and then operate s in fifo mode, collecting new samples only when fifo is not full. a delay of at least 5 s should be present between the trigger event occurring and the start of reading data from the fifo to allow the fifo to discard and retain the necessary samples. additional trigger events can not be recognized until the trigger mode is reset. to reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode . note that t he fifo data should be read first because placing the device into bypass mode clear s fifo. retrieving data from fifo the fifo data is read through the datax, datay , and dataz registers ( address 0x32 to address 0x37) . when the fifo is in fifo, stream , or trigger mode , reads to the datax, datay, and dataz registers read data stored in the fifo. each time data is read from the fifo , the oldest x - , y - , and z - axes data are placed into the datax, datay , and dataz registers. if a single - byte read operation is performed, the remaining bytes of data for the current fifo sample are lost. therefore, all axes of interest shou ld be read in a burst (or multi ple - byte) read operation. to ensure that the fifo has completely popped (that is, that new data has completely moved into the datax , data y, and data z registers ) , there must be at least 5 s between the end of reading the data registers and the start of a new read of the fifo or a read of the fifo_status regi ster (address 0x39) . the end of reading a data register is signified by the transition from register 0x37 to register 0x38 or by the cs pin going high. for spi operation at 1.6 mhz or less , the register addressing portion of the trans mission is a sufficient delay to ensure that the fifo has completely popped. for spi operation greater than 1.6 mhz, it is necessary to de assert the cs pin to ensure a total delay of 5 s ; otherwise, the delay is not sufficient . the t otal delay necessary for 5 mhz operation is at most 3.4 s. this is not a concern when using i 2 c mode because the communication rate is low enough to ensure a sufficient delay between fifo reads.
ADXL343 preliminary technical data rev. pra | page 20 of 36 self - test the ADXL343 incorporates a self - test feature that effectively tests its mechanical and electronic systems simultaneously . when the self - test function is enabled (via the self_test bit in the data_format register , address 0x31 ), an electrostatic force is exe rted on the mechanical sensor. this electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. this added electrostatic force results in an output change in the x - , y - , and z - axes. because the electrostatic force is proportional to v s 2 , the output change varies with v s . this effect is shown in figure 33 . the scale factors shown in table 14 can be used to ad just the expected self - test output limits for different supply voltages , v s . the self - test featu re of the ADXL343 also exhibits a bi modal behavior . h owever, the limits shown in table 1 and table 15 to table 18 are valid for both potential self - test values due to bimodality . use of the self - test feature at data rates less than 100 hz or at 1600 hz may yiel d values outside these limi ts. therefore, the part must be in normal power operation (low_power bit = 0 in bw_rate register, address 0x2c) and be placed into a data rate of 100 hz through 800 hz or 3200 hz for the self - test function to operate correctly. ?6 ?4 ?2 0 2 4 6 2.0 2.5 3.3 3.6 v s (v) self-test shift limit ( g) x high x low y high y low z high z low 10627-242 figure 33 . self - test output change limits vs. supply voltage table 14. self - test output scale factors for different supply voltages, v s supply voltage, v s (v) x- axis , y - ax is z - axis 2.00 0.64 0.8 2. 50 1.00 1.00 3.30 1.77 1.47 3 .60 2.11 1.69 table 15. self - test output in lsb for 2 g , 10 - bit or full resolution (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) axis min max unit x 50 540 lsb y ? 540 ? 5 0 lsb z 75 875 lsb table 16. self - test output in lsb for 4 g , 10 - bit resolution (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) axis min max unit x 25 270 lsb y ? 270 ? 25 lsb z 38 438 lsb table 17. self - test output in lsb for 8 g , 10 - bit resolution (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) axis min max unit x 12 135 lsb y ? 135 ? 12 lsb z 19 219 lsb table 18 . self - test output in lsb for 16 g , 10 - bit resolution (t a = 25c, v s = 2.5 v , v dd i/o = 1.8 v) axis min max unit x 6 67 lsb y ? 67 ? 6 lsb z 10 110 lsb
preliminary technical data ADXL343 rev. pra | page 21 of 36 register map table 19. address hex dec name type reset value description 0x0 0 0 devid r 111001 01 device id 0x0 1 to 0x1c 1 to 28 reserved reserved; do not access 0x 1d 29 thresh_tap r/ w 00000000 tap threshold 0x 1e 30 ofsx r/ w 00000000 x - axis offset 0x 1f 31 ofsy r/ w 00000000 y - axis offset 0x 20 32 ofsz r/ w 00000000 z - axis offset 0x 21 33 dur r/ w 00000 000 tap duration 0x 22 34 latent r/ w 00000000 tap latency 0x 23 35 window r/ w 00000000 tap window 0x 24 36 thresh_act r/ w 00000000 activity threshold 0x 25 37 thresh_inact r/ w 00000000 inactivity threshold 0x 26 38 time_inact r/ w 00000000 inactivity time 0x 27 39 act_inact_ctl r/ w 00000000 axis enable control for activity and inactivity detection 0x 28 40 thresh_ff r/ w 00000000 free - fall th reshold 0x 29 41 time_ff r/ w 00000000 free - fall time 0x 2a 42 tap_axes r/ w 00000000 axis control for single tap/double tap 0x 2b 43 act_tap_status r 00000000 source of single ta p/double tap 0x 2c 44 bw_rate r/ w 00001010 d ata rate and power mode control 0x 2d 45 power_ctl r/ w 00000000 power - saving features control 0x 2e 46 int_enable r/ w 00000000 interrupt enable co ntrol 0x 2f 47 int_map r/ w 00000000 interrupt mapping control 0x 30 48 int_source r 0000001 0 source of interrupts 0x 31 49 data_format r/ w 00000000 data format control 0x 32 50 datax0 r 00000000 x - axis data 0 0x 33 51 datax1 r 00000000 x - axis data 1 0x 34 52 datay0 r 00000000 y - axis data 0 0x 35 53 datay1 r 00000000 y - axis data 1 0x 36 54 dataz0 r 00000000 z - axis data 0 0x 37 55 dataz1 r 00000000 z - axis data 1 0x 38 56 fifo_ctl r / w 00000000 f ifo control 0x 39 57 fifo_status r 00000000 fifo status
ADXL343 preliminary technical data rev. pra | page 22 of 36 register definitions register 0x00 devid ( read only ) d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 0 0 1 0 1 the devid register holds a fixed device id code of 0xe5 (345 octal). register 0x1d thresh_tap ( read/ write ) the thresh_tap register is eight bits and holds the threshold value for tap interrupts. the data format is unsigned, therefore, the magnitude of the tap event is compared with the value in thresh_tap for normal tap detection. the scale factor is 62 .5 m g / lsb (that is , 0xff = 16 g ). a value of 0 may result in undesirable behavior if single tap/double tap interrupts are enabled. register 0x1e, register 0x1f, register 0x20 ofsx, ofsy, ofsz ( read/write ) the ofsx, ofsy, and ofsz registers are each eight bits and offer user - set offset adjustments in twos compl e ment form at with a scale factor of 15.6 m g /lsb ( that is , 0x7f = 2 g ). the value stored in the offset registers is automatically added to the acceleration data , and the resulting value is stored in th e output data registers. for additional information regarding offset calibration and the use of the offset registers, refer to the offset calibration section. register 0x21 dur ( read/write ) the dur register is eight bits and conta ins an unsigned time value representing the maximum time that an event must be above the thresh_tap threshold to qualify as a tap event. the scale factor is 625 s/lsb. a value of 0 disables the single tap/ double tap functions. register 0x22 latent ( read/ write ) the latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detec ted . the scale factor is 1.25 ms/lsb. a value of 0 disable s the double tap function. register 0x23 window ( read/write ) the window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register ) during which a second valid tap can begin. the scale factor is 1.25 ms/lsb. a value of 0 disable s the double tap function. register 0x24 thresh_act ( read/write ) the thresh_act register is eight bits and holds the t hreshold value for detecting activity. the data format is unsigned, therefore, the magnitude of the activity event is compared with the value in the thresh_act register . the scale factor is 62.5 m g /lsb. a value of 0 may result in undesirable behavior if the activity interrupt is enabled. register 0x25 thresh_inact ( read/write ) the thresh_inact register is eight bits and holds the threshold value for detecting inactivity. the data format is unsigned, therefore, the magnitude of the inactivity event is comp ared with the value in the thresh_inact register . the scale factor is 62.5 m g /lsb. a value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. register 0x26 time_inact ( read/write ) the time_inact register is eight bits and con tains an unsigned time value representing the amount of time that acceleration must be less than the value in the thresh_inact register for inactivity to be declared. the scale factor is 1 sec/lsb. unlike the other interrupt functions, which use unfiltered data ( see the threshold section), the inactivity function uses filtered output data. at least one output sample must be generated for the inactivity interrupt to be triggered. this result s in the function appearing un responsive if the time_inact register is set to a value less than the time constant of the output data rate . a value of 0 result s in an interrupt when the output data is less than the value in the thresh_inact register . register 0x27 act_inact_c tl ( read/write ) d7 d6 d5 d4 act ac/dc act_x enable act_y enable act_z enable d3 d2 d1 d0 inact ac/dc inact_x enable inact_y enable inact_z enable act ac/dc and inact ac/dc bits a setting of 0 selects dc - coupled operation , and a setting of 1 enables ac - coupled operation. in dc - coupled operation, the current acceleration magnitude is compared directly with thresh_act and thresh_inact to determine whether activity or inactivity is detected. in ac - coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. new samples of acceleration are then compared to this reference value , and if the magnitude of the difference exceeds the thresh_act value , the device trigger s an activity interrupt. similarly, i n ac - c oupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. after the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with thresh_inact . if the difference is less than the value in thresh_inact for the time in time_inact , the device is considered inactive and the inactivity interrupt is triggered.
preliminary technical data ADXL343 rev. pra | page 23 of 36 act_x enable bits and in act_x enable bits a setting of 1 enables x - , y - , or z - axis participation in detecting activity or inactivity. a setting of 0 excludes the selected axis from participation. if all axes are excluded, the function is disabled. for activity detection, all part icipating axes are logically ored, causing the activity function to trigger when any of the partici - pating axes exceeds the threshold. for inactivity detection, all participating axes are logically anded, causing the inactivity function to trigger only i f all participating axes are below the threshold for the specified time . register 0x28 thresh_ff ( read/write ) the thresh_ff register is eight bits and holds the threshold v alue , in unsigned format, for free - fall detection. the acceleration on all axes is c ompared with the value in thresh_ff to determine if a free - fall event occurred . the scale factor is 62.5 m g /lsb. note that a value of 0 m g may result in undesirable behavior if the free - fall interrupt is enabled . value s between 300 m g and 600 m g (0x05 to 0 x09) are recommended. register 0x29 time_ff ( read/write ) the time_ff register is eight bits and stores an unsigned time value representing the minimum time that the value of all axes must be less than thresh_ff to generate a free - fall interrupt. the scale factor is 5 ms/lsb. a value of 0 may result in undesirable behavior if the free - fall interrupt is enabled. values between 100 ms and 350 ms (0x14 to 0x46) are recommended. register 0x2a tap_axes ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 suppress tap_x enable tap_y enable tap_z enable suppress bit setting the suppress bit suppresses double tap detection if acceleration greater than the value in thresh_tap is present between taps. see the tap detection s ection for more details. tap_x enable bits a setting of 1 in the tap_x enable, tap_y enable, or tap_z enable bit enables x - , y - , or z - axis participation in tap detection. a setting of 0 excludes the selected axis from participation in tap detection. register 0x2b act_tap_status ( read only ) d7 d6 d5 d4 d3 d2 d1 d0 0 act_x source act_y source act_z source asleep tap_x source tap_y source tap_z source act_x source and tap_x source bits these bits indicate the first axis involved in a tap or activity event. a setting of 1 correspon ds to involvement in the event , and a setting of 0 corresponds to no involvement. when new data is available, t hese bits are not cleared but are overwritten by the new data. the act_tap_status register should be read before clearing the interrupt. disablin g an axis from participation clear s the corresponding source bit when the next activity or single tap/double tap event occurs. a s leep bit a setting of 1 in the asleep bit indicates that the part is asleep , and a setting of 0 indicates that the part is not asleep . this bit toggle s only if the device is configured for auto sleep. see the auto_sleep bit section for more information on auto sleep mode . register 0x2c bw_rate ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 low_power rate l ow_power bit a setting of 0 in the low_power bit selects normal operation , and a setting of 1 selects reduced power operation , which has somewhat higher noise ( s ee the power modes section for details). rate bits these bits select the device b andwidth and output data rate (s ee table 7 and table 8 for details ) . the d efault value is 0x0a, which translates to a 100 hz output data rate . an output data rate should be selected that is appropriate for the communication protocol and frequency selected. selecting too high of an output data rate with a low communication speed result s in samples being discarded. register 0x2d power_ctl ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 0 0 link auto_slee p measure sleep wakeup link bit a setting of 1 in the link bit with both the activity and inactivity functions enabled delay s the start of the activity function until inactivity is detected. after activity is detected, inactivity detection begin s , preven t ing the detection of activity. this bit serially links the activity and inactiv ity functions. when this bit is set to 0 , the inactivity and activity functions are concurrent. additional information can be found in the link mode section . when clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; ot herwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. auto_sleep bit if the link bit is set, a setting of 1 in the auto_sleep bit enables the auto - sleep functionality. in this mode, the ADXL343 auto - matically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, when acceleration is below the thresh_inact value for at least the time indicated by time_inact). if activity is also enabled, the ADXL343 automatically wake s up from sleep after detecting activity and return s to operation at the output data rate set in the bw_ra te register. a setting of 0 in the auto_sleep bit disables automatic switching to sleep mode. see the description of the sleep bit in this section for more information on sleep mode.
ADXL343 preliminary technical data rev. pra | page 24 of 36 if the link bit is not set, the auto_sleep fea ture is disabled and s etting the auto_sleep bit does not have an impact on device operation. refer to the link bit section or the link mode section for more information on utilization of the link feature. when clearing the auto_sleep bit, it is recommended that the part be placed into standby mode and then set back to measure - ment mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; oth erwise, the first few samples of data after the auto_sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared . measure bit a setting of 0 in the measure bit places th e part into standby mode, and a settin g of 1 places the part into measurement mode. the ADXL343 powers up in standby mode with minimum power consumption. sleep bit a setting of 0 in the sleep bit puts the part into the normal mode of operation, a nd a setting of 1 places the part into sleep mode. sleep mode suppresses data_ready, stops transmission of data to fifo, and switches the sampling rate to one specified by the w akeup bits. in sleep mode, only the activity function can be used. whe n the dat a_ready interrupt is suppressed, the output data registers ( register 0x32 to register 0x37) are still updated at the sampling rate set by the wakeup bits (d1:d0) . when clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. this is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, espe cially if the device was asleep when the bit was cleared . wa k eu p bit s the s e bit s c ontrol the frequency of readings in sleep mode as described in table 20. table 20. freq uency of readings in sleep mode sett ing d1 d0 frequency (hz) 0 0 8 0 1 4 1 0 2 1 1 1 register 0x2e int_enable ( read/write ) d7 d6 d5 d4 data_ready single_tap double_tap activity d3 d2 d1 d0 inactivity free_fall watermark overrun setting bits in this register to a value of 1 enable s their respective functions to generate interrupts , whereas a value of 0 prevent s the functions from generating interrupt s. the data_ready, watermark , and overrun bits enable only the interrupt output; the functions are always enabled. it is recomm ended that interrupts be configured before enabling their outputs. register 0x2f int_map ( read/write ) d7 d6 d5 d4 data_ready single_tap double_tap activity d3 d2 d1 d0 inactivity free_fall watermark overrun any bits set to 0 in this register send thei r respecti ve interrupts to the int1 pin, whereas b its set to 1 send their respective interrupts to the int2 pin. all selected interrupts for a given pin are or ed. register 0x30 int_source ( read only ) d7 d6 d5 d4 data_ready single_tap double_tap activity d3 d2 d1 d0 inactivity free_fall watermark overrun bits set to 1 in this register indicate that their resp ective functions have triggered an event , whereas a value of 0 indicates that the corresponding event has not occurred. the data_ready, watermark , and overrun bits are always set if the corresponding event s occur , regardless of the int_enable register settings , and are cleared by reading data from the datax, data y, and data z registers. the data_ready and watermark bits may require multiple reads, as indicated in the fifo mode descriptions in the fifo section. other bits, and the corresponding interrupts, are cleared by reading the int_source register . register 0x31 data_format ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 self_test spi int_invert 0 full_res justify range the data_format register con trols the presentation of data to register 0x32 through register 0x37. all data, except that for the 16 g range, must be clipped to avoid rollover. self_test bit a setting of 1 in the self_test bit applies a self - test force to the sensor , causing a shift in the output data. a value of 0 disable s the self - test force . spi bit a value of 1 in the spi bit sets the devic e to 3 - wire spi mode , and a value of 0 se ts the device to 4 - wire spi mo de .
preliminary technical data ADXL343 rev. pra | page 25 of 36 int_invert bit a value of 0 in the int_invert bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low . full_res bit when this bit is set to a value of 1 , the device is in full resolution mode , where the output resol ution increases with the g range set by the range bits to maintain a 4 m g /lsb scale factor. when the full_res bit is set to 0 , the device is in 10 - bit mode , and the range bits determine the maximum g range and scale factor. justify bit a setting of 1 in th e justify bit selects left - justified (msb) mode , and a setting of 0 selects right - justified mode with sign extension. range bits these bits set the g range as described in table 21. table 21. g range setti ng setting d1 d0 g range 0 0 2 g 0 1 4 g 1 0 8 g 1 1 16 g register 0x32 to register 0x3 7 datax0, datax1 , datay0, datay1, dataz0, dataz1 ( read only ) these six bytes (register 0x32 to register 0x37) are eight bits each and hold the output data fo r ea ch axis . register 0x32 and register 0x33 hold the output data for the x - axis, register 0x34 and register 0x35 hold the output data for the y - axis, and register 0x36 and register 0x37 hold the output data for the z - axis. the output data is two s compleme nt , with datax0 as the least significant byte and datax1 as the most significant byte , where x represent x, y, or z . the data_format register ( address 0x31) controls the format of the data. it is recommended that a multi ple - byte read of all registers be pe rformed to prevent a change in data between reads of sequential registers. register 0x38 fifo_ctl ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 fifo_mode trigger samples fifo_mode bits the se bits set the fifo mode , as described in table 22. table 22 . fifo modes setting d7 d6 mode function 0 0 bypass fifo is bypassed. 0 1 fifo fifo collects up to 32 values and then stops collecting data, collecting new data only when fifo is not full. 1 0 stream fifo hol ds the last 32 data values. when fifo is full, the oldest data is overwritten with newer data. 1 1 trigger when triggered by the trigger bit, fifo holds the last data samples before the trigger event and then continues to collect data until full. new data is collected only when fifo is not full. trigger bit a value of 0 in the trigger bit links the trigger event of trigger mode to int1 , and a value of 1 links the trigger event to int2. samples bits the f unction of these bits depends on the fifo mode sele cted (see table 23) . entering a value of 0 in the samples bits immedi - ately set s the watermark status bit in the int_source register , regardless of which fifo mode is selected . undesirable operation may occur if a value of 0 is u sed for the samples bits when trigger mode is used. table 23. samples bits functions fifo mode samples bits function bypass none. fifo specifies how many fifo entries are needed to trigger a watermark interrupt. stream specifies how many fifo entries are needed to trigger a watermark interrupt. trigger specifies how many fifo samples are retained in the fifo buffer before a trigger event. 0x39 fifo_status ( read only ) d7 d6 d5 d4 d3 d2 d1 d0 fifo_trig 0 entries fifo_ trig bit a 1 in the fifo_trig bit corresponds to a t rigger event occurring, and a 0 means that a fifo trigger e vent has not occurred. entries bits these bits report how many data values are stored in fifo. access to collect the data from fifo is provided through the datax, datay, and dataz registers. fifo reads must be done in burst or multi ple - byte mode because each fifo level is cleared a fter any read ( single - or multi ple - byte) of fifo. fifo stores a maximum of 32 entries, which equates to a maximum of 33 entr ies a vailable at any given time because an additional entry is available at the output filter of the device.
ADXL343 preliminary technical data rev. pra | page 26 of 36 application s information power supply decoupl ing a 1 f tantalum capacitor (c s ) at v s and a 0.1 f ceramic capacitor (c i / o ) at v dd i/o placed close t o the ADXL343 supply pins is recommended to adequately decouple the accelerometer from noise on the power supply. if additional decoupling is necessary, a resistor or ferrite bead, no larger than 1 0 0 ?, in series with v s may be helpful. additionally, increasing the bypass capacitance on v s to a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor may also improve noise. care should be taken to ensure that the connection from the ADXL343 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through v s . it is recommended that v s and v dd i/o be separate supplies to minimize digital clocking noise on the v s supply. if this is not possible, additional filtering of the supplies , as previously mentioned , may be necessary. ADXL343 gnd int1 int2 cs scl/sclk sdo/alt address sda/sdi/sdio 3- or 4-wire spi or i 2 c interface v s v s c s v dd i/o v dd i/o c io interrupt control 10627-016 figure 34 . application diagram mechanical considera tions for mounting the ADXL343 should be mounted on the pcb in a location close to a hard mounting point of the pcb to the case. mounting the ADXL343 at an unsupported pcb location , as shown in figure 35 , may result in large , apparent measurement errors due to undampened pcb vibration . locating the accelerometer near a hard mounting point ensures that any pcb vibration at the accelerometer is above the ac celerometers mechanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. multiple mounting points close to the sensor and/or a thicker pcb also help to reduce the effect of system resonance on the performance of the se nsor. mounting points pcb accelerometers 10627-036 figure 35 . incorrectly placed accelerometer s tap detection the tap interrupt function is capable of detecting either single or double taps. the following parameters are shown in figure 36 for a v alid single and valid double tap event: ? t he t ap detection threshold is defined by the thresh_tap register (address 0x1 d ) . ? the m aximum tap duration time is defined by the dur register (address 0x21) . ? t he t ap latency time is defined by the latent register ( address 0x22) and is the waiting period from the end of the first tap until the start of the time window, when a second tap can be detected, which is determined by the value in the window register (address 0x23) . ? the interval after the latency time (set b y the latent register) is defined by the window register . although a second tap must begin after the latency time has expired, it need not finish before the end of the time defined by the window register . first tap time limit for taps (dur) latency time (latent) time window for second tap (window) second tap single tap interrupt double tap interrupt threshold (thresh_tap) x hi bw interrupts 10627-037 figure 36 . tap interrupt function with valid single and double taps if only the single tap function is in use, the single tap interrupt is trigger ed when the acceleration goes below the threshold , as long as dur has not been exceeded. if both single and double tap functions are i n use , the single tap interrupt is trigger ed when the double tap event has been either validated or invalidated.
preliminary technical data ADXL343 rev. pra | page 27 of 36 several events can occur to invalidate the second tap of a double tap event. first, if the suppress bit in the tap_axes register (address 0x2a ) is set, any acceleration spike above the threshold during the latency time (set by the latent register) invalidate s the double tap detection , as shown in figure 37. invalidates double tap if supress bit set time window for second tap (window) latency time (latent) time limit for taps (dur) x hi bw 10627-038 figure 37 . double tap event invalid due to high g event when the suppress bit is set a double tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap (set by the window register) . this result s in an invalid double tap at the start of this window , as shown in figure 38. additionally, a double tap event can be invalidated if an accel - eration exceed s the time limit for taps (set by the dur register) , resulting in an invalid double tap at the end of the dur time limit for the second tap event, also shown in figure 38. invalidates double tap at start of window time window for second tap (window) latency time (latent) invalidates double tap at end of dur time limit for taps (dur) time limit for taps (dur) time limit for taps (dur) x hi bw x hi bw 10627-039 figure 38 . tap interrupt function with invalid double taps single taps, double taps, or both can be detected by setting the respective bits in the int_enable register (address 0x2e) . control over participation of each of the three axes in single tap/ double tap detection is exerted by setting the appropriate bits in the tap_axes register (address 0x2a) . for the double tap funct ion to operate, both the latent and window registers must be set to a non zero value . every mechanical system has somewhat different single tap/ double tap response s based on the mechanical characteristics of the system . therefore, some experimentation with values for the dur, latent , window , and thresh_tap registers is required. in general , a good starting point is to set the dur register to a value greater than 0x10 (10 ms), the latent register to a value greater than 0x10 (20 ms) , the window register to a value greater than 0x4 0 (80 ms) , and the thresh_tap register to a value greater than 0x30 ( 3 g ) . setting a very low value in the latent, window , or thresh_tap register may result in an unpredictable response due to the accelerometer picking up echoes of the tap inputs. after a tap interrupt has been received, the first axis to exceed the thresh_tap level is reported in the act_tap_status register (address 0x2b) . this register is never cleared but is overwritten with new data. threshold the lower output da ta rates are achieved by decimati ng a common sampling frequency inside the device. the activity, free - fall , and single tap/double tap detection funct ions without improved tap enabled are performed using undecimated data . because the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data , the high frequency and high g data that is used to determine activity, free - fall , and single tap/double tap events may not be present if the output of the acceleromet er is examined. this may result in functions triggering when acceleration data does not appear to meet the conditions set by the user for the corresponding function. link mode the function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity. for proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the int_source register (address 0x30) and, therefore, clear ing the interrupts . if an activity interrupt is not cleared, the part can not go into auto sleep mode . the asleep bit in the act_tap_status register (address 0x2b) indicates if the part is asleep .
ADXL343 preliminary technical data rev. pra | page 28 of 36 sleep mode vs. l ow power mode in applications where a low data rate and low power consumption is desired (at the expense of noise performance), it is recommended that low power mode be used. the use of low power mode preserves the functionality of the data_ready interrupt and fifo for pos t processing of the acceleration data. sleep mode, while offering a low data rate and power consumption, is not intended for data acquisiti on. however, when sleep mode is used in conjunction with the auto_sleep mode and the link mode, the part can automatic ally switch to a low power, low sampling rate mode when inactivity is detected. to prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and activity is enabled. when the ADXL343 is in sleep mode, the host processor can also be placed into sleep mode or low power mode to save significant system power. when activity is detected, the accelerometer automatically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor. similar to when inactivity occurs, detection of activity events is disabled and inactivity is enabled. offset calibration accelerometers are mechanical structur es containing elements that are free to move. these moving parts can be very sensitive to mechanical stresses, much more so than solid - state electronics. the 0 g bias or offset is an important accelerometer metric because it define s the baseline for measur ing acceleration. additional stresses can be applied during assembly of a system containing an accelerometer. these stresses can come from, but are not limited to, component soldering, board stress during mounting, and application of any compounds on or ov er the component. if calibration is deemed necessary, it is recommended that calibration be performed after system assembly to compensate for these effects. a simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL343 is as specified in table 1 . the offset can then be automatically accounted for by using the built - in offset registers. this results in the data acquired from the data registe rs already compensating for any offset. in a no - turn or single - point calibration scheme, the part is oriented such that one axi s, typically the z - axis, is in the 1 g field of gravity and the remaining axes, typically the x - and y - axis, are in a 0 g field. the output is then measured by taking the average of a series of samples. the number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 hz or greater . this corresponds to 10 samples at the 100 hz data rate. for data rates less than 100 hz, it is recommended that at least 10 samples be averaged together. these values are stored as x 0 g , y 0 g , and z +1 g for the 0 g measurements on the x - and y - axis and the 1 g measurement on the z - axis, respectively. the value s measured for x 0 g and y 0 g correspond to the x - and y - axis offset , and compensation is done by subtracting those values from the output of the accelerometer to obtain the actual acceleration: x actual = x meas ? x 0 g y actual = y meas ? y 0 g because the z - axis measurement was done in a +1 g field, a no - turn or single - point calibration scheme assumes an idea l sensitivity, s z for the z - axis. this is subtracted from z +1 g to attain the z - axis offset , which is then subtr acted from future measured values to obtain the actual value: z 0 g = z +1 g ? s z z actual = z meas ? z 0 g t he ADXL343 can automatically compensate the output for offset by using the offset registers (register 0x1e, register 0x1f , and register 0x20). these registers contain an 8 - bit, two s complement value that is automatically added to all measured acceleration values , and the result is then placed into the data registers. because the value placed in an offset registe r is additive, a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset . the register has a scale factor of 15.6 m g /lsb and is independent of the selected g - range. as an example, assume that the ADXL343 is placed into full - resolution mode with a sensitivity of typically 256 lsb/ g . the part is oriented such that the z - axis is in the field of gravity and x - , y - , and z - axis outputs are measured as +10 lsb, ? 1 3 lsb, and +9 lsb , respectively. using the previous equations, x 0 g is + 10 lsb, y 0 g is ? 13 lsb , and z 0 g is +9 lsb. each lsb of output in full - resolution is 3.9 m g or one - quarter of a n lsb of the offset register. because the offset register is additive , the 0 g values are negated and rounded to the nearest lsb of the offset register: x offset = ? round (10/4) = ? 3 lsb y offset = ? round ( ? 13/4) = 3 lsb z offset = ? round (9/4) = ? 2 lsb the se values are programmed into the ofsx, ofsy , and ofxz register s, respectively, as 0xfd, 0x03 , and 0xfe . as with all registers in the ADXL343 , the offset registers do not retain the value written into them when p ower is removed from the part. power - cycling the ADXL343 return s the offset registers to their default value of 0x00. because the no - turn or single - point calibration method assumes an ideal sensitivity in the z - axis, any error in the sensitivit y result s in offset error. for instance, i f the actual sensitivity was 250 lsb/ g in the previous example, the offset would be 15 lsb , not 9 lsb. to help minimize this error, an additional measurement point ca n be used with the z - axis in a 0 g field and the 0 g measurement can be used in the z actua l equation.
preliminary technical data ADXL343 rev. pra | page 29 of 36 using self - test the self - test change is defined as the difference between the acceleration output of an axis with self - test enabled and the acceleration output of the same axis with self - test disabled (see endnote 4 of table 1 ) . this definition assumes that the sensor does not move between these two measurements. if the sensor moves, the additional shift, which is unrelated to self - test, corrupts the test. p roper configuration of the ADXL343 is also necessary for an accurate self - test measurement. the part should be set w ith a data rate of 100 hz through 800 hz, or 3200 hz . this is done by ensuring that a value of 0x0a through 0x0d, or 0x0f is wri tten into the rate bits ( bit d3 through bit d0) in the bw_rate register ( address 0x 2c). the part also must be placed into normal power operation by ensuring the low_power bit in the bw_rate register is cleared (low_power bit = 0) for accurate self - test measurements . it is recommen ded that t he part be set to full - resolution , 16 g mode to ensure that there is sufficient dynamic range for the entire self - test shift. this is done by setting bit d3 of the data_format register ( address 0x31) and writing a value of 0x03 to the range bits (bit d1 and bit d0) of the data_format register ( address 0x31). this results in a high dynamic range for measurement and a 3.9 m g /lsb scale factor. after the part is configured for accurate self - test measurement, several samples of x - , y - , and z - axis accel eration data should be retrieved from the sensor and averaged together. the number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 s ec worth of data for data rates of 100 hz or greater . this corresponds to 1 0 samples at the 100 hz data rate. for data rates less than 100 hz, it is recommended that at least 10 samples be averaged together. the averaged values should be stored and labeled appropriately as the self - test disabled data, that is, x st_off , y st_off , and z st_off . next, self - test should be enabled by setting bit d7 (self_test) of the data_format register ( address 0x31). the output needs some time (about four samples) to settle after enabling self - test . after allowing the output to settle, several sampl es of the x - , y - , and z - axis acceleration data should be taken again and averaged. it is recommended that the same number of samples be taken for this average as was previously taken. these averaged values should again be stored and labeled appropriately a s the value with self - test enabled, that is, x st_on , y st_on , and z st_on . self - test can then be disabled by clearing bit d7 (self_test) of the data_format register ( address 0x31). with the stored values for self - test enabled and disabled, the self - test chan ge is as follows : x st = x st_on ? x st_off y st = y st_on ? y st_off z st = z st_on ? z st_off because the measured output for each axis is expressed in lsbs, x st , y st , and z st are also expressed in lsbs. t hese values can be converted to g s of acceleration by mul tiplying each value by the 3. 9 m g /lsb scale factor , if configured for full - resolution mode. additionally, table 15 through table 18 correspond to the self - test range converted to lsbs and can be compare d with the measured self - test change when operating at a v s of 2.5 v . for other voltages, the minimum and maximum self - test output values should be adjusted based on (multiplied by) the scale factors shown in table 14 . if the par t was placed into 2 g , 10 - bit or full - resolution mode, the values listed in table 15 should be used. although t he fixed 10 - bit mode or a range other than 16 g can be used, a different set of values, as indicated in table 16 through table 18 , would need to be used. using a range below 8 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self - test. if the self - test change is within the valid range, the test is considered successful. generally, a part is considered to pass if the minimum magnitude of change is achieved. however, a part that changes by more than the maximum magnitude is not necessarily a failure. another effective method for using the self - test to verify accel - erometer functionality is to toggle the self - test at a certain rate and then perform an fft on the output. the fft should have a correspond ing tone at the frequency the self - test was toggle d. using an fft like this removes the dependency of the test on supply voltage and on self - test magnitude, which can vary within a rather wide range.
ADXL343 preliminary technical data rev. pra | page 30 of 36 data formatting of u pper data rates formatting of output data at the 3200 hz and 1600 hz output data r ates changes depending on the mode of operation (full - resolution or fixed 10 - bit) and the selected output range. when using the 3200 hz or 1600 hz output data rates in full - resolution or 2 g, 10 - bit operation, the lsb of the output data - word is always 0. when data is right justified, this corresponds to bit d0 of the datax0 register, as shown in figure 39 . when data is left justified and the part is operating in 2 g, 10 - bit mode, the lsb of the output data - word is bit d6 of the d atax0 register. in full - resolution operation when data is left justified, the location of the lsb changes according to the selected output range. for a range of 2 g, the lsb is bit d6 of the datax0 register; for 4 g, bit d5 of the datax0 register; for 8 g, bit d4 of the datax0 register; and for 16 g, bit d3 of the datax0 register. this is shown in figure 40. the use of 3200 hz and 1600 hz output data rates for fixed 10- bit operation in the 4 g, 8 g, and 16 g output ranges provides an lsb that is valid and that changes according to the applied acceleration. therefore, i n these modes of operation, bit d0 is not always 0 when output data is right justified and bit d6 is not always 0 when output data is left justified. operatio n at any data rate of 800 hz or lower also provides a valid lsb in all ranges and modes that changes according to the applied acceleration. 0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 datax1 register datax0 register output data-word for 16 g , full-resolution mode. output data-word for all 10-bit modes and the 2 g, full-resolution mode. the 4 g and 8 g full-resolution modes have the same lsb location as the 2 g and 16 g full-resolution modes, but the msb location changes to bit d2 and bit d3 of the datax1 register for 4 g and 8 g, respectively. 10627-145 figure 39 . data formatting of full - resolution and 2 g , 10 - bit modes of operation wh en output data is right justified 0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 datax1 register datax0 register msb for all modes of operation when left justified. lsb for 2 g , full-resolution and 2 g , 10-bit modes. lsb for 4 g , full-resolution mode. lsb for 8 g , full-resolution mode. lsb for 16 g , full-resolution mode. for 3200hz and 1600hz output data rates, the lsb in these modes is always 0. additionally, any bits to the right of the lsb are always 0 when the output data is left justified. 10627-146 figure 40 . data formatting of full - resolution and 2 g , 10 - bit modes of operation when output data is left justified
preliminary technical data ADXL343 rev. pra | page 31 of 36 noise performance the specification of noise shown in table 1 corresponds to the typical noise performance of the ADXL343 in normal power oper ation with an output data rate of 100 hz (low_power bit (d4) = 0, rate bits (d3:d0) = 0xa in the bw_rate register, address 0x2c). for normal power operation at data rates below 100 hz, the noise of the ADXL343 is equivalent to the noise at 100 hz odr in lsbs. for data rates greater than 100 hz, the noise increases roughly by a factor of 2 per doubling of the data rate. for example, at 400 hz odr, the noise on the x - and y - axes is typically less than 1.5 lsb rms, and the noise on the z - axis is typically less than 2.2 lsb rms. for low power operation (low_power bit (d4) = 1 in the bw_rate register, address 0x2c), the noise of the ADXL343 is constant for all valid data rates shown in table 8 . this value is typically less than 1.8 lsb rms for the x - and y - axes and typically less than 2.6 lsb rms for the z - axis. the trend of noise performance for both normal power and low power modes of operation of the ADXL343 is shown in figure 41. figure 42 shows the typical allan deviation for the ADXL343 . the 1/f corner of the device, as shown in this figure, is very low, allowing absolute resolution of approximately 100 g (assuming that there is sufficient integration time). figure 42 also sho ws that the noise density is 290 g /hz for the x - axis and y - ax i s and 4 30 g/hz for the z - axis. figure 43 shows the typical noise performance trend of the ADXL343 over supply voltage. the performance is normalized to the tested and specified supply voltage, v s = 2.5 v. in general, n ois e decreases as supply voltage is increased . it should be noted , as shown in figure 41 , that the noise on the z - axis is typically higher than on the x - axis and y - ax i s ; therefore, while they change roughly the same in percentage over supply voltage, the magnitude of change on the z - axis is greater than the magnitude of change on the x - axis and y - ax i s. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 3.13 6.25 12.50 25 50 100 200 400 800 1600 3200 output d at a r a te (hz) output noise (lsb rms) x-axis, norma l power x-axis, low power y -axis, norma l power y -axis, low power z-axis, norma l power z-axis, low power 10627-250 figure 41 . noise vs. output data ra te for normal and low power modes, full - resolution (256 lsb/g) 0.01 0.1 1 10 100 1k 10k 10 100 1k 10k a veraging period, (s) allan devi a tion ( g) x-axis y -axis z-axis 10627-251 figure 42 . root allan deviation 70 80 90 100 1 10 120 130 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supp l y vo lt age, v s (v) percen t age of normalized noise (%) x-axis y -axis z-axis 10627-252 figure 43 . normalized noise vs. supply voltage , v s operation at voltage s other than 2.5 v the ADXL343 is tested and specified at a supply voltage of v s = 2.5 v; however, it can be powered with v s as high as 3.6 v or as low as 2.0 v. some performance parameters change as the supply voltage changes: offset, sensit ivity, noise, self - test , and supply current. due to slight changes in the electrostatic forces as supply voltage is varied, the offset and sensitivity change slightly. when operating at a supply voltage of v s = 3.3 v, the x - and y - axis offset is typically 25 m g higher than at vs = 2.5 v operation. the z - axis is typically 20 m g lower when operating at a supply voltage of 3.3 v than when operating at v s = 2.5 v. sensitivity on the x - and y - axes typically shifts from a nominal 256 lsb/ g (full - resolution or 2 g , 10 - bit operation) at v s = 2.5 v operation to 265 lsb/ g when operating with a supply voltage of 3.3 v. the z - axis sensitivity is unaffected by a change in supply voltage and is the same at v s = 3.3 v operation as it is at v s = 2.5 v operation. simple lin ear interpolation can be used to determine typical shifts in offset and sensitivity at other supply voltages.
ADXL343 preliminary technical data rev. pra | page 32 of 36 changes in noise performance, self - test response, and supply current are discussed elsewhere throughout the data sheet. for noise performance, the noise performance section should be reviewed. the using self - te st section discusses both the operation of self - test over voltage, a square relationship with supply voltage, as well as the conversion o f the self - test response in g s to lsbs. finally, figure 23 shows the impact of supply voltage on typical current consumption at a 100 hz output data rate, with all other output data rates following the same trend. offset performa nce at lowest data r ates the ADXL343 offers a large number of output data rates and bandwidths, designed for a large range of applications. however, at the lowest data rates, described as those data rates belo w 6.25 hz, the offset performance over temperature can vary significantly from the remaining data rates. figure 44 , figure 45, and figure 46 show the typical offset performance of the ADXL343 over temperature for the data rates of 6.25 hz and lower. all plots are normalized to the offset at 100 hz output data rate; therefore, a nonzero value corresponds to additional offset shift due to temperature for that data rate. when using the lowest data rates, it is recommended that the operating temperature range of the device be limited to provide minimal offset shift across the operating temperature range. due to variability between part s, it is also recommended that calibration over temperature be performed if any data rates below 6.25 hz are in use. 0 20 40 60 80 100 120 140 25 35 45 55 65 75 85 normalized output (lsb) temper a ture (c) 0.10hz 0.20hz 0.39hz 0.78hz 1.56hz 3.13hz 6.25hz 10627-056 figure 44 . typical x - axis output vs. temperature at lower data rates, normalized to 100 hz output data rate, v s = 2.5 v 0 20 40 60 80 100 120 140 25 35 45 55 65 75 85 normalized output (lsb) temper a ture (c) 0.10hz 0.20hz 0.39hz 0.78hz 1.56hz 3.13hz 6.25hz 10627-057 figure 45 . typical y - axis output vs. temperature at lower data rates, normalized to 100 hz output data rate, v s = 2.5 v ?20 0 20 40 60 80 100 120 140 25 35 45 55 65 75 85 normalized output (lsb) temper a ture (c) 0.10hz 0.20hz 0.39hz 0.78hz 1.56hz 3.13hz 6.25hz 10627-058 figure 46 . typical z - axis output vs. temperature at lower data rates, nor malized to 100 hz output data rate, v s = 2.5 v
preliminary technical data ADXL343 rev. pra | page 33 of 36 axes of acceleration sensitivity a z a y a x 10627-021 figure 47 . axes of acceleration sensitivity (corresponding output voltage increases when accelerated along the sensitive axis) gravity x out = 1 g y out = 0 g z out = 0 g top x out = ?1 g y out = 0 g z out = 0 g top x out = 0 g y out = 1 g z out = 0 g top x out = 0 g y out = ?1 g z out = 0 g top x out = 0 g y out = 0 g z out = 1 g x out = 0 g y out = 0 g z out = ?1 g 10627-022 figure 48 . output response vs. orientation to gravity
ADXL343 preliminary technical data rev. pra | page 34 of 36 layout and design re commendations figure 49 shows the recommended pr inted wiring board land pattern. figure 50 and table 24 provide details about the recommended soldering profile. 3.3400 0.5500 0.2500 3.0500 0.2500 1.1450 5.3400 1.0500 10627-014 figure 49 . recommended printed wiring board land pattern (dimensions shown in millimeters ) t p t l t 25c to peak t s preheat critical zone t l to t p temperature time ramp-down ramp-up t smin t smax t p t l 10627-015 figure 50 . recommended soldering pro file table 24. recommended soldering profile 1, 2 condition profile feature sn63/pb37 pb - free averag e ramp rate from liquid temperature ( t l ) to peak temperature ( t p ) 3c/sec max imum 3c/sec maximum preheat minimum temperatur e (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time from t smin to t smax (t s ) 60 sec to 120 sec 60 sec to 180 sec t smax to t l ramp - up rate 3c/sec maximum 3c/sec maximum liquid temperature (t l ) 183c 217c time maintained above t l (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240 + 0/?5c 260 + 0/?5c time of actual t p ? 5c (t p ) 10 sec to 30 sec 20 sec to 40 sec ramp - down rate 6c/sec maximum 6c/sec maximum time 25c to peak temperature 6 minutes maximum 8 minutes maximum 1 based on jedec standard j - std - 020d.1. 2 for best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder pa ste used.
preliminary technical data ADXL343 rev. pra | page 35 of 36 outline dimensions bottom view top view end view seating plane 1.00 0.95 0.85 5.00 bsc 3.00 bsc pad a1 corner 0.79 0.74 0.69 1 6 7 8 14 13 0.80 bsc 1.01 1.50 0.49 0.50 0.49 0.813 0.50 03-16-2010-a figure 51. 14-terminal land grid array [lga] (cc-14-1) solder terminations finish is au over ni dimensions shown in millimeters
ADXL343 preliminary technical data rev. pra | page 36 of 36 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . analog devices offers specific products designated for automotive applications; please consult your local analog devices sale s representative for details. standard products sold by anal og devices are not designed, intended, or approved for use in life support, implantable medical devices, transportation, nucl ear, safety, or other equipment where malfunction of the product can reasonably be expected to result in personal injury, death, se vere property damage, or severe environmental harm. buyer uses or sells standard products for use in the above critical applications at buyer's own risk and buyer agrees to defend, indemnify, and hold harmless analog device s from any and all damages, claim s, suits, or expenses resulting from such unintended use. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr10627 - 0 - 5/12(pra)

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